发明名称 State engine for data processor
摘要 The ordering of packet flows, comprising sequences of data packets, in a communication or computer system, is performed by assigning an exit number to each packet; queuing the packets in a buffer; and outputting the queued packets in a predetermined order according to an order list determined by the exit numbers assigned to each packet before it was queued. The exit number information is preferably assigned to packet records, which are queued in a separate buffer to the packets, the records being of fixed length and shorter than the data portions. The packet record buffer comprises groups of bins, each bin containing a range of exit numbers, the bins for higher exit number packet records having a larger range than bins for lower exit number packet records. Lower exit number packet records in a bin are subdivided into a plurality of bins, each containing packet records corresponding to a smaller range of exit numbers. Secondary bins may be created to temporarily store records assigned to a bin that is currently being emptied. The bins may be filled by a parallel processor, preferably a SIMD array processor.
申请公布号 GB2411271(B) 申请公布日期 2006.07.26
申请号 GB20050009997 申请日期 2003.11.11
申请人 CLEARSPEED TECHNOLOGY PLC 发明人 ANTHONY SPENCER
分类号 G06F9/46;G06F15/80;H04L12/56 主分类号 G06F9/46
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