发明名称 |
Inspection pattern, inspection method, and inspection system for detection of latent defect of multi-layer wiring structure |
摘要 |
An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.
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申请公布号 |
US7081758(B2) |
申请公布日期 |
2006.07.25 |
申请号 |
US20050037131 |
申请日期 |
2005.01.19 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
UMEMURA EIICHI;FUKUNAGA HIROYUKI;NAKAYASHIKI HIROYUKI |
分类号 |
G01R31/02;G01R31/28;H01L21/66;H01L21/768;H01L21/822;H01L23/522;H01L23/544;H01L23/58;H01L27/04 |
主分类号 |
G01R31/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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