Memory apparatus wherein the logical sum of address and data is stored at two addressable locations,申请号US19630254986-传众专利搜索

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发明名称	Memory apparatus wherein the logical sum of address and data is stored at two addressable locations
摘要
申请公布号	US3274562(A)	申请公布日期	1966.09.20
申请号	US19630254986	申请日期	1963.01.30
申请人	SPERRY RAND CORPORATION	发明人	STRAWBRIDGE GEORGE B.
分类号	G06F7/38;G06F17/30	主分类号	G06F7/38
代理机构		代理人
主权项
地址

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