| 摘要 |
PROBLEM TO BE SOLVED: To form an extension portion of an optimal junction depth even if a gate length is extremely short. SOLUTION: In a method for manufacturing an insulated gate field effect transistor, two source-drain regions 10 are formed in a P well 3 by performing impurity ion implantation and activation annealing while using a gate stack 7 and a spacer of a sidewall insulating film 9 having a predetermined width as a mask. Subsequently, the sidewall insulating film 9 is removed and a thin barrier insulating film 11 is formed, thus retracting both sides of the spacer in the width direction. Consequently, the edge of the spacer and the edge of the source-drain region 10 are separated on both the sides in the width direction. In this state, a semiconductor material is grown by selective epitaxial growth in a well region exposed to both the sides of the spacer in the width direction and including two source-drain regions 10 thus forming two extension portions 12 separated by the retracted spacer. In the manufacturing method, impurities in the extension portion 12 are not thermally diffused into the P well 3 by activation annealing for ion implantation. COPYRIGHT: (C)2006,JPO&NCIPI
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