| 摘要 |
To generate a spread frequency spectrum clock signal in a digital approach permitting to make the key parameters independent of process, temperature and supply voltage variations, a digital phase locked loop is used. In a first step (a), a clock signal at a maximum clock frequency is generated. In a second step (b), the clock frequency is stepwise reduced by incrementally adding phase delay steps to the clock signal until a minimum clock frequency is reached. In a further step (c), the number of incrementally added phase delay steps is stepwise reduced until the maximum clock frequency is reached. Steps (a) to (c) are continuously repeated.
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