| 摘要 |
Provided is an external memory accessing architecture for use with IC comprising a first bus connected to an external memory and having n-bit data width; a first buffer unit of k serially connected first buffers each having n-bit data width, a first one of the first buffers connected to the external memory via the first bus; a second buffer unit comprising a second buffer having k*n-bit data width, the second buffer connected to the first buffers; a second bus connected to the second buffer for transferring k*n-bit data; an output unit connected to the second buffer unit and comprising a multiplexer; and a controller connected to the output unit, the second bus, and the external memory respectively such that the controller is able to read data from the external memory or transfer data thereto via the second bus and at least one control signal in higher transfer rate.
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