发明名称 PLL frequency synthesizer architecture for low phase noise and reference spurs
摘要 A frequency synthesizer for use in a transceiver generates a relatively high reference frequency with fine frequency resolution and low in-band phase noise by using a digital processor to generate a digital reference signal at a finely-tuned reference frequency. A Digital-to-Analog Converter (DAC) converts the digital reference signal to an analog reference signal, and a low pass filter filters the analog reference signal to produce a filtered analog reference signal. The frequency synthesizer further includes a phase locked loop for up-converting the filtered analog reference signal from an IF signal to an RF signal.
申请公布号 US2006160492(A1) 申请公布日期 2006.07.20
申请号 US20050039116 申请日期 2005.01.20
申请人 JENSEN HENRIK T 发明人 JENSEN HENRIK T.
分类号 H04B1/40;H01Q11/12;H04B1/04 主分类号 H04B1/40
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