| 摘要 |
PROBLEM TO BE SOLVED: To disclose a technology for enhancing retaining characteristics in a nano scale charge trap insulator memory and increasing a cell integration capacity by stacking a large number of charge trap insulator cell arrays in the vertical direction using a large number of cell insulation layers. SOLUTION: The charge trap insulator memory comprises a lower word line, a P type float channel for retaining a floating state formed above the lower word line, a charge trap insulator formed above the P type float channel and storing data, an upper word line formed above a charge trap insulator in parallel with the lower word line, and an N type drain region and an N type source region formed on both sides of the float channel. COPYRIGHT: (C)2006,JPO&NCIPI
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