发明名称 |
Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time |
摘要 |
A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.
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申请公布号 |
US2006157822(A1) |
申请公布日期 |
2006.07.20 |
申请号 |
US20060330194 |
申请日期 |
2006.01.12 |
申请人 |
KAWASAKI MICROELECTRONICS, INC. |
发明人 |
KUNITOMO HIROYASU;NIMURA TOMOAKI;KUNO ISAMU;ARIYOSHI RYUJI |
分类号 |
H01L29/00 |
主分类号 |
H01L29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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