| 摘要 |
PROBLEM TO BE SOLVED: To disclose a technology for enhancing retaining characteristics in a nano scale charge trap insulator memory and increasing a cell integration capacity by stacking a large number of charge trap insulator cell arrays in the vertical direction using a large number of cell insulation layers. SOLUTION: The charge trap insulator memory comprises a large number of memory cells coupled in series where data stored in a charge trap insulator are outputted to a bit line, a first switching element for coupling the bit line and the large number of memory cells selectively depending on the state of a first select signal, a second switching element for coupling the sensing line and a plurality of memory cells selectively depending on the state of a second select signal, a P type float channel having a resistance variable depending on the polarity of the charge trap insulator, and a P type drain region and a P type source region formed on both sides of the P type float channel. COPYRIGHT: (C)2006,JPO&NCIPI
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