发明名称 TEST SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a test system using a JTAG (joint test action group) extension interface provided by expanding a conventional JTAG, making the best use of an existing resource. SOLUTION: A boundary scan pass chain (BSPC) is formed of a plurality of input circuits 40in, and a plurality of output circuits 40out. This system includes a substitution bus 32a of a test bus substituted by one portion or the whole of an existing I/O bus. An initial state is assigned by circulating a data of each of the circuits 40in in the BSPC when testing a tested system such as a logic circuit 31, the data of the respective circuits 40in are read into a shift register in its inside, or a data of the respective circuits 40out are read into the shift register in its inside, after operating a system clock sck, and the clock sck is operated to read out the data of circuits 40in or the circuits 40out from the BSCP. A permission data is circulated in the BSCP, and the data of the circuits 40out are read out to the substitution bus 32a only when the permission data is effective. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006189368(A) 申请公布日期 2006.07.20
申请号 JP20050002553 申请日期 2005.01.07
申请人 OKI ELECTRIC IND CO LTD 发明人 HORIE KIMITO
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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