| 摘要 |
The invention relates to a semiconductor wafer ( 1 ) having a plurality of first sawing regions ( 201 - 211 ) running parallel to one another in a first direction (X) and a plurality of second sawing regions ( 301 - 311 ) running parallel to one another in a second direction (Y), having useful regions ( 10 ) which in each case contain an integrated circuit ( 100 ) and which are in each case arranged between respective adjacent first sawing regions ( 201 - 211 ) and respective adjacent second sawing regions ( 301 - 311 ), and at least one test structure region arranged in the first sawing regions ( 201 - 211 ) and the second sawing regions ( 301 - 311 ) with test structures formed therein for checking electrical parameters of semiconductor elements. Connection contacts ( 51 - 54 ) connected to the test structures are provided in the test structure region, which connection contacts form a first row (R 1 ) and a second row (R 2 ), which in each case run in a longitudinal direction (L) and are offset relative to one another in the longitudinal direction (L) and transversely with respect to the longitudinal direction (L).
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