| 摘要 |
An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.
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