| 摘要 |
PROBLEM TO BE SOLVED: To improve verification coverage with respect to the function of a verification scenario, and detect LSI design faults accurately and efficiently, by estimating an upper limit of code coverage. SOLUTION: A verification support device 200 substitutes an undefined value x for a variable in a verification scenario S, in a substitution part 202, when the verification scenario S is acquired in an acquisition part 201. In a first execution part 211, logical simulation is executed by use of an input pattern PX. From the execution result, code coverage upper limit information CM is generated in a determination part 205. In a setting part 203, input patterns P1 and P2 are set by substituting an arbitrary logical value for/in a variable in the verification scenario S. In a second execution part 212, logical simulation is executed by use of the input patterns P1 and P2. In a generation part 206, code coverage CC is generated from the input patterns P1 and P2, and, in a calculation part 207, a code coverage attainment rate with respect to the code coverage upper limit information CM is calculated. COPYRIGHT: (C)2006,JPO&NCIPI
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