| 摘要 |
One embodiment of the present invention provides a system that avoids write-after-read (WAR) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. While deferring the instruction, the system stores the instruction along with any resolved source operands for the instruction into a deferred buffer. |
