发明名称 |
Analog delay locked loop having duty cycle correction circuit |
摘要 |
An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.
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申请公布号 |
US7078949(B2) |
申请公布日期 |
2006.07.18 |
申请号 |
US20030750243 |
申请日期 |
2003.12.31 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM SE-JUN;HONG SANG-HOON;KO JAE-BUM |
分类号 |
G06F1/04;H03L7/06;G11C11/407;H03K5/05;H03K5/135;H03L7/00;H03L7/07;H03L7/08;H03L7/081 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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