Semiconductor memory device with back gate potential control circuit for transistor in memory cell

摘要

A substrate potential setting circuits are provided which control substrate potentials in units of columns of a memory cell array at least in data writing. Upon data writing, the potential of the substrate region of memory cell transistors on a selected column is changed to reduce the data holding characteristics (static noise margin) to ensure high-speed data writing to the memory cells. Data writing is performed at high speed without impairing stability of data retention.