| 摘要 |
A method and apparatus for compensating address and control lines to account for clock delays within a memory device is disclosed. Latches are located directly within a the storage area of the memory device, so that the parasitic capacitance inherent within the address and control lines can be advantageously employed for introducing delay. The parasitic delay enables the clock, address, and control lines to be synchronized, yet does not require introducing delay blocks and so the overall speed of the memory device is improved.
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