发明名称 System for monitoring a period of an operation clock signal of a CPU and stopping operations of the CPU when the period is out of a predetermined allowable range
摘要 There is provided a technology for preventing disabling of function of a clock monitoring circuit by a hacker in a microcomputer for IC card provided with a clock monitoring circuit as a countermeasure for a hacker. In the microcomputer for IC card provided with the clock monitoring circuit, the clock monitoring circuit is given the function to perform the detecting operation twice during one cycle, namely at the timings of rise and fall of the clock.
申请公布号 US7080001(B2) 申请公布日期 2006.07.18
申请号 US20030372970 申请日期 2003.02.26
申请人 HITACHI ULSI SYSTEMS CO., LTD. 发明人 MORIYAMA NAOKATSU;SHINOHARA SHIGERU
分类号 B42D15/10;G08B21/00;G06F1/04;G06F1/24;G06F12/14;G06F21/00;G06F21/24;G06K19/07;G06K19/073 主分类号 B42D15/10
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