发明名称 |
Expanded comparator for control of digital delay lines in a delay locked loop or phase locked loop |
摘要 |
A digital delay locked loop (DLL) includes a phase detector that measures the phase difference between a signal to be synchronized and a reference signal. The phase detector produces an increase or decrease signal in response to the phase difference between the two signals. This signal is received by a binary counter, which changes its count in response. The output of the binary counter is supplied to a comparator logic that implements a thermometer coding scheme. Each of the comparator output signals enables or disables a corresponding transistor stack in a delay line, thereby changing the delay of the signal propagating through the delay line.
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申请公布号 |
US7079615(B2) |
申请公布日期 |
2006.07.18 |
申请号 |
US20010988691 |
申请日期 |
2001.11.20 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
BAILEY DANIEL WILLIAM |
分类号 |
H03D3/24;H03K5/00;H03K5/13;H03L7/081;H03L7/089;H03L7/093 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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