发明名称 |
Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor |
摘要 |
Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.
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申请公布号 |
US2006155961(A1) |
申请公布日期 |
2006.07.13 |
申请号 |
US20050030339 |
申请日期 |
2005.01.06 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DIEFFENDERFER JAMES N.;DOING RICHARD W.;PATEL SANJAY B.;TESTA STEVEN R.;TSUCHIYA KENICHI |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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