| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce writing and erasing time of a highly integrated flash memory. <P>SOLUTION: The highly integrated flash memory is provided with many flash memory cells 2nk which are arranged in a matrix manner and made programmable, word lines WLi and bit lines BLi which connect the memory cells, verify cells 4n each of which is connected to the word lines, has the same structure of the memory cell and has a couple ratio that is made different from the memory cell, a verify means which verifies the verify cells, and a reading means which reads the output of the verify cell, that is connected to a selected word line, through a bit line. The verify cells 4n are connected by a common bit line BLvi. The reading means includes a reference cell 16 that generates a reference signal and a comparing circuit which compares the reference signal from the reference cell with the output of the verify cell. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
