| 摘要 |
PROBLEM TO BE SOLVED: To provide a ferroelectric memory which is small in area for an element and reduced in read error. SOLUTION: This ferroelectric memory has 1st memory cells connected to 1st bit lines and 1st plate lines, 2nd memory cells connected to 2nd bit lines and the 1st plate lines, a plate line control circuit to control voltages of the 1st plate lines based on plate line control signals, a delay circuit to form expected delay signals which delays the plate line control signals, capacitors provided between the 1st bit lines and the delay circuit to change the voltages of the 1st bit lines based on the delay signals, and a sense amplifier to determine data stored in the 2nd memory cells by comparing the voltages of the 1st bit lines and the 2nd bit lines. COPYRIGHT: (C)2006,JPO&NCIPI
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