发明名称 |
Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip |
摘要 |
An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.
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申请公布号 |
US2006156100(A1) |
申请公布日期 |
2006.07.13 |
申请号 |
US20040023731 |
申请日期 |
2004.12.28 |
申请人 |
BOIKE MARK A;KALLURI SESHAGIRI P;ANGARAI VIJAYANAND J;BRANTLEY DAVID M;BEEKER SCOTT A |
发明人 |
BOIKE MARK A.;KALLURI SESHAGIRI P.;ANGARAI VIJAYANAND J.;BRANTLEY DAVID M.;BEEKER SCOTT A. |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
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