| 摘要 |
PROBLEM TO BE SOLVED: To realize efficient memory access without degrading the performance of a latency sensitive master. SOLUTION: In a memory access control circuit, an arbiter 4 (transaction detection means) detects that a transaction from a bus master (the latency sensitive master) which influences the performance by latency has been registered in a queueing buffer 5, and the arbiter 4 (processing sequence change means) processes this transaction prior to transactions queued in advance. COPYRIGHT: (C)2006,JPO&NCIPI
|
