| 摘要 |
<P>PROBLEM TO BE SOLVED: To stably generate a signal synchronously with a reference signal at a high speed. <P>SOLUTION: A phase difference count section 15a counts a phase difference between the reference signal f1 and a frequency division signal f2 to produce a phase difference count C. A threshold value discrimination section 15b compares the phase difference count C with a threshold value to produce a phase difference discrimination signal D2 denoting whether or not the phase difference count C exceeds the threshold value. When recognizing an outside range of the threshold value indicating that the phase difference count C exceeds the threshold value on the basis of the phase difference discrimination signal D2, a phase shift processing section 16 carries out phase shift processing for forcibly shifting a phase of the frequency division signal f2 so as to make the phase difference zero on the basis of the phase difference count C thereby allowing the PLL unit to start PLL feedback control from a state of zero phase difference. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
