Dual stage DRAM memory equalization

摘要

A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the conventional equilibrate process so that the positive portion and the negative portion of the sense amplifier are equilibrated at different times. Bit line equilibration can be associated with either the equilibrate step associated with the positive portion of the sense amplifier or the equilibrate step associated with the negative portion of the sense amplifier.