| 摘要 |
A method of reducing hardware overhead upon the generation of a test pattern in a built-in self test is introduced, in which two pieces of hardware perform a lot of functions even prior to generation of deterministic patterns, thereby reducing the amount of hardware required for conventional pseudo-random pattern generation while not increasing test time appreciably. This method is characterized in that an LFSR is constructed such that it shifts only one bit among N-1 bits taken from the N bits of an N bit-pattern counter and bit counter to a scan chain.
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