发明名称 High-speed track and hold architectures
摘要 A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i-1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i-1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.
申请公布号 US2006152393(A1) 申请公布日期 2006.07.13
申请号 US20050284985 申请日期 2005.11.21
申请人 发明人 GUPTA SANDEEP K.;ZABRODA OLEKSLY
分类号 H03M7/00 主分类号 H03M7/00
代理机构 代理人
主权项
地址