| 摘要 |
An integrated semiconductor memory device includes memory cells which are connected to first sense amplifiers or second sense amplifiers via in each case one bit line pair. During a read access of one of the memory cells, the sense amplifier connected to the memory cell to be read out evaluates a cell voltage of the memory cell to be read out and generates a data item with a logical Low or High level depending on the level of the cell voltage at a data terminal. However, if the sense amplifiers are not of identical construction or arrangement, the same cell voltage level is evaluated differently by the first sense amplifier than by the sense amplifier. To match the evaluation performance of the first and second sense amplifiers, the connected bit line pairs are precharged to different precharging voltages before a read access.
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