EFFICIENT SWITCHING BETWEEN PRIORITIZED TASKS

摘要

The present invention relates to a processor device, task scheduling method and computer program product, wherein tasks of a program routine are selectively stored in at least two memory stack mechanisms (62, 64) of different priorities based on the allocated priorities. Switching of tasks executed at at least two processor means (20, 30) is controlled by accessing the at least two memory stack mechanisms (62, 64) in response to synchronization instructions inserted to the program routine. Thereby, efficient zero-cycle task switching between prioritized tasks can be achieved.