| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit in which increase in circuit scale can be suppressed while suppressing increase in current consumption. <P>SOLUTION: The flip-flop circuit comprises a delay latch circuit 2a including inverter circuits 6 and 7, and an n-channel transistor 4 for equalizing the potential at the output node of the inverter circuit 6 and the potential at the output node of the inverter circuit 7. The delay latch circuit 2a is connected with a power source line for supplying power supply voltages VSPM and VSNM which can make a switch between a potential being supplied when the potential at the output node of the inverter circuit 6 and the potential at the output node of the inverter circuit 7 are fixed, and a potential being supplied when the output node of the inverter circuit 6 and the output node of the inverter circuit 7 are floated. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
