发明名称 Output power testing apparatus for memory
摘要 An output power testing apparatus for memory is provided. The apparatus includes a signal control device and an adjusting voltage circuit. The signal control device is coupled to the adjusting voltage circuit, and the adjusting voltage circuit adjusts the output voltage based on a set of testing signals from the signal control device.
申请公布号 US2006152985(A1) 申请公布日期 2006.07.13
申请号 US20050236500 申请日期 2005.09.28
申请人 INVENTEC CORPORATION 发明人 CHEN MEI-HUI
分类号 G11C7/00;G11C29/00 主分类号 G11C7/00
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