| 摘要 |
An integrated semiconductor memory device includes sense amplifiers that are connected to in each case one bit line pair via controllable voltage generators. In a test mode state, precharging voltages can be fed to at least one of the bit lines of each one of the bit line pairs via the controllable voltage generators. The level of the precharging voltage is dependent on a data item present at a data terminal. The precharging voltages of a bit line pair can be transferred to an adjacent bit line pair via a coupling unit. In a subsequent evaluation process, the prepared precharging voltages are evaluated by the connected sense amplifier.
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