| 摘要 |
1,140,685. Multiplex pulse code signalling. NIPPON TELEGRAPH & TELEPHONE PUBLIC CORP. 25 Jan., 1966 [1 Feb., 1965], No. 3261/66. Heading H4L. Means are provided for returing a plurality of asynchronous pulse code communication systems so that they may be arranged in frames and transmitted on a common time division multiplex system. Frame synchronizing pulses are inserted and additional "redundancy" pulses may be inserted in the pulse trains of each individual system so that the clock frequencies are made equal, these additional pulses being removed at the demultiplexing station. General arrangement, Fig. 1 (not shown).- The asynchronous pulse inputs (1 to 1 m ) are applied to respective pulse retiming circuits (3) inserting the additional pulses as required, and controlled by a master clock (4) the phasing of the retimed circuits being arranged to facilitate time division multiplexing at (5). Each circuit (3) includes a temporary store from which the pulses are read out at a frequency slightly higher than the pulse rate of the corresponding input signal (1) &c. At the receiver, timing information is extracted from the signal at (8) and controls the demultiplexer (7). Retiming circuits (9) remove the inserted pulses and supply the asynchronous pulse trains to the respective output terminals (Z 1 to Z m ). Transmitter retiming circuit (3), Fig. 3.-The incoming asynchronous pulse code train is supplied via terminal 1 to a temporary store 12, clock signals being extracted at 11 to control the write-in to the store 12. The read-out from the store 12 via OR gate 18 is controlled by pulses from the common clock 4 supplied via INHIBIT gate 13. The insertion of the additional synchronizing, &c. pulses is controlled by a signal from store 12 via terminal 23 indicating that the stored signals have been reduced to less than a predetermined amount. A counter 14 counts up to a predetermined number of clock pulses supplied via INHIBIT gate 13 and then triggers a flip-flop 15, the resulting signal blocking the gate 13 so that counter 14 and the read-out from store 12 are stopped. The output from flip-flop 15 is also applied to an AND gate 16 so that clock pulses from 4 are supplied to a frame synchronizing signal generator 17 generating a sync. signal composed of one bit, which is delayed by one time slot if a signal is present at terminal 23. This sync. signal is fed via OR gate 18 to the output 10 and coincident with the trailing edge of the last pulse of the sync. signal a signal from terminal 29 resets flip-flop 15 so that counting and read-out is resumed. Receiver retiming circuit (9), Fig. 4.-A pulse code train from the demultiplexer is fed to a store 34 and clock pulses are extracted from the pulse train at 32. The clock pulses are applied via an AND gate 33 to a counter 35 and also control the write-in to the store 34. At a predetermined count (equal to that of counters 14) flip-flops 36, 37 are set so that AND gate 33 is blocked, monostable device 47 is set, and a signal is passed via INHIBIT gate 39, one-time slot delay 40 and OR gate 41 to AND gate 42 so that after a 1 bit delay the pulse signal (normally the sync. signal) is supplied to a sync. pattern recognizer 43 which supplies an output signal when the trailing edge of the last pulse of the sync. signal is detected. This output from 43 resets flip-flop 37 and flip-flop 36 via OR gate 44 so that clock signals are again passed by AND gate 33 to operate the counter 35 and store 34. If synchronizing is correct, when flip-flop 37 is set, its output is passed via a three-bit delay 45 and INHIBIT gate 46 to gates 38 and 39 but during the period when flip-flop 36 is set there will be no output from gate 46 due to the 3-bit delay. If the synchronizing code is not detected at 43 flip-flops 36, 37 are not reset and the signal from monostable device 47, which extends over three time slots, is supplied to differentiator 48 which provides a trigger signal when the monostable device resets. This trigger signal is supplied via INHIBIT gate 49 and OR gate 44 to reset the flip-flop 36 one time slot later than it would normally be reset. Flip-flop 37 remains set during the next frame and its output via delay 45 and gate 46 inhibits the gate 39 so that the signal when flip-flop 36 is set again is supplied via AND gate 38 and OR gate 41 to control the sync. pattern recognizer 43. This instant corresponds to the first time slot of the sync. code so that it can be detected if present. The presence of a continuous signal at the output of flip-flop 37 for more than three frames is detected at 50 and this is taken to mean a loss of framing rather than a temporary interruption. An output from 50 inhibits gates 49, 46 so that flip-flops 36, 37 are reset only by a signal from sync. pattern recognizer 43 and in this way hunting for the sync. signal is initiated. When frame sync. is recovered there is no output from circuit 50 and the retiming circuit returns to normal. If frame sync. signal consisting of two successive bits is used as in Fig. 2 (not shown), an additional flip-flop is provided which is connected one time slot earlier than the flipflop 36 to the counter 35. |
