发明名称 |
VIDEO SIGNAL PROCESSOR |
摘要 |
<p>In the case of performing NR (noise reduction) and scaling on video signals, the NR buffer 104 is formed by, for example, five line memories. An NR section 103 and a scaling section 105 are controlled by a control section 108. The control section 108 controls the NR section 103 and the scaling section 105 such that video signals subjected to noise reduction by the NR section 103 and corresponding to one line are output from the NR section 103 to an arbitrary one of the line memories of the NR buffer 104 and video signals corresponding to a plurality of lines and stored in the line memories of the NR buffer 104 except for the line memory to which the video signals corresponding to one line have been input from the NR section 103 are input from the NR buffer 104 to the scaling section 105. Accordingly, noise components of video signals are reduced with the memory size reduced.</p> |
申请公布号 |
EP1679882(A1) |
申请公布日期 |
2006.07.12 |
申请号 |
EP20050776888 |
申请日期 |
2005.09.01 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
YAMANA, AKIFUMI;HOASHI, KATSUMI |
分类号 |
H04N5/21;G09G5/00;G09G5/18;G09G5/36;H04N5/262;H04N5/66;H04N7/01 |
主分类号 |
H04N5/21 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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