| 摘要 |
A nonvolatile ferroelectric memory device transmits/receives data of a cell by using a main bitline of a cell array block as a data bus in a system on chip (SOC) having a hierarchical bitline structure, thereby reducing the chip size. In the nonvolatile ferroelectric memory device, when an interface is performed between a logic processor and a cell array block, cell data and amplification data of a sense amplifier are transmitted into an I/O port interface unit by using a main bitline of the cell array block as a data bus, thereby improving the data access speed and reducing the whole chip size.
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