| 摘要 |
An A/D converter includes at least one comparator array (COMP 1 -COMP 7 ) for flash A/D conversion of an analog signal. Means (CCU, SW 1 -SW 7 ) provide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC 1 -DAC 7 ) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC 1 -DAC 7 ) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.
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