Delta-sigma modulated fractional-N PLL frequency synthesizer and wireless communication apparatus

摘要

Disclosed is a delta-sigma modulated fractional-N PLL frequency synthesizer which performs fractional-N by modulating a divider that divides output frequencies from a voltage controlled oscillator. Fractional part data F from a register is forwarded to a second adder. A first adder adds output from a delta-sigma modulator to output therefrom delayed and inverted by a delay inverter to generate an artificially random bit stream averaging zero. The second adder adds fractional part data F to output from the first adder to generate an artificially random data sequence averaging a value of fractional part data. The generated data sequence is forwarded to the delta-sigma modulator. An adder adds integral part data to output from the delta-sigma modulator. Added output is forwarded to the divider.