发明名称 Method and apparatus for evaluating logic states of design nodes for cycle-based simulation
摘要 A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.
申请公布号 US7076416(B2) 申请公布日期 2006.07.11
申请号 US20020105754 申请日期 2002.03.25
申请人 SUN MICROSYSTEMS, INC. 发明人 CHEN LIANG T.;LAM WILLIAM KWEI-CHEUNG;MCWILLIAMS THOMAS M.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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