发明名称 |
Generating a test sequence using a satisfiability technique |
摘要 |
Generating a test sequence includes receiving a circuit representation describing a circuit, and a fault associated with the circuit representation. A miter circuit model associated with a good circuit model and a faulty circuit model is established according to the circuit representation. A satisfiability problem corresponding to the fault as associated with the miter circuit model is also established. Whether the satisfiability problem is satisfiable is determined. If the satisfiability problem is satisfiable, a test sequence is generated for the fault as associated with the miter circuit model.
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申请公布号 |
US7076712(B2) |
申请公布日期 |
2006.07.11 |
申请号 |
US20030444483 |
申请日期 |
2003.05.22 |
申请人 |
FUJITSU LIMITED |
发明人 |
PRASAD MUKUL R.;HSIAO MICHAEL S.;JAIN JAWAHAR |
分类号 |
G06F11/00;G01R31/3183;G01R31/3185 |
主分类号 |
G06F11/00 |
代理机构 |
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主权项 |
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