发明名称 VARIABLE BIT RATE CODING APPARATUS
摘要 A cumulative error D is calculated by sequentially adding up errors, each representing a difference between a given average target number Ba and a number Bg of bits generated during every predetermined period of a coded bit stream. In determining a number Bt of bits allocated to a compression coder, a provisionally allocated bit number Bst is preset based on a coding complexity X such that a number of bits allocated to a scene with a high coding complexity exceeds the average target number Ba as for a frame just after the change of scenes. And if the cumulative error D exceeds a predetermined value, the provisionally allocated bit number Bst is corrected in accordance with the magnitude of the cumulative error D so as to be reducible to, but not less than, the average target number Ba. As for frames within the same scene on the other hand, a previously allocated bit number Bt is sequentially updated such that the cumulative error D does not exceed a predetermined maximum value Dmax. Accordingly, even if a series of scenes with high coding complexities X appear consecutively, a number Bt of bits allocated to each of these scenes can always be at least equal to the average target number Ba, while the total number of bits generated can also be regulated. As a result, high image quality is ensured.
申请公布号 KR100598293(B1) 申请公布日期 2006.07.07
申请号 KR19990041650 申请日期 1999.09.29
申请人 发明人
分类号 H04N7/30;H04N7/26 主分类号 H04N7/30
代理机构 代理人
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