Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby

摘要

In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes a semiconductor substrate having buried contact landing pads and direct contact landing pads. A lower interlayer insulating layer is disposed on the semiconductor substrate. A plurality of parallel bit line patterns are disposed on the lower interlayer insulating layer to fill the direct contact holes. A passivation layer that conformally covers the lower interlayer insulating layer and the bit line patterns is formed. An upper interlayer insulating layer for covering the semiconductor substrate having the passivation layer is formed. Buried contact plugs are disposed in the upper interlayer insulating layer between the bit line patterns and extended to contact the respective buried contact landing pads through the passivation layer and the lower interlayer insulating layer. Voids are formed in the upper interlayer insulating layer between the bit line patterns and between the buried contact plugs.