Apparatus and method for latency control in high frequency synchronous semiconductor device

摘要

An apparatus for controlling a latency in a synchronous semiconductor device. The apparatus includes a first counting block for counting a cycle of a first clock signal to thereby generate a first binary code; a second counting block for counting a cycle of a second clock signal to thereby generate a second binary code. The second clock signal is obtained by delaying the first clock signal by a predetermined delay amount, A code comparison block stores the second binary code in response to a command and compares the first binary code with the second binary code to thereby generate a latency control signal.