| 摘要 |
<p>A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier. Sample capacitors and reference capacitors receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors are provided to maintain constant circuit gain. Extended reference voltages (V <SUB>REFNX</s</p> |
