| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a CMOS type SRAM cell that enables access of higher speed. <P>SOLUTION: Since, the gate of an nMOS transistor QN1 and the gate of a pMOS transistor QP1 are composed of a polysilicon wiring G10, the gate of an nMOS transistor QN2 and the gate of a pMOS transistor QP2 are composed of a polysilicon wiring G20, the gates of nMOS transistors QN3 and QN4 are composed of polysilicon wirings W10 and W20, respectively, the poly silicon wirings G10 and W20 are aligned and arranged in a first direction extending from an nMOS region 13A to an nMOS region 13B, and the poly silicon wirings G20 and W10 are aligned and arranged in the first direction, the length of a bit line extending in a second direction perpendicular to the first direction, becomes to that of two transistors. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
