| 摘要 |
PROBLEM TO BE SOLVED: To reduce test cost by fitting a physical position of a regular memory cell where data are read or written to a physical position of a parity memory cell. SOLUTION: A normal writing data selection circuit 10 operates in a normal operating mode and outputs data received by an external data terminal DQ to either of regular cell arrays CA 1-4 selected according to an address AD. A test writing control circuit 12 operates in a test mode and in each regular cell array CA 1-4, writes test data in a regular memory cell at a position corresponding to the position of the parity memory cell where test parity data are written. Therefore, a common test pattern can be used in order to test a regular memory cell and a parity memory cell, and the test cost can be reduced. COPYRIGHT: (C)2006,JPO&NCIPI
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