LOGIC CIRCUITRY

摘要

A logic circuit (100) including at least one evaluate circuit (130) coupled to a static output logic circuit (190). In one example, the evaluate circuit (130) includes a dynamic node (139), a full keeper (132), an evaluate device (136), and a logic tree (134). In some examples, the output logic circuit is a sampled static output logic circuit (150) and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits (140), each with a dynamic node (149) coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay (180) in a clock signal to increase the internal race margin.