发明名称 CACHE COHERENCE SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To reduce the load of a snoop bus connecting a plurality of cache units and a memory management unit(directory side) at a main storage side. <P>SOLUTION: When latest data are not stored in a main storage 28, but stored in a plurality of cache units 18, one of the plurality of cache units owns a write ownership for copying the latest data back to the main storage 28. In this status, when the replacement of the latest data is generated by a processor 16 by the cache unit having the write ownership, the write ownership is transferred to the cache unit having the latest data, and the copy back of the latest data to the main storage 28 is suppressed from being performed until the cache unit owning the latest data becomes one. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006179033(A) 申请公布日期 2006.07.06
申请号 JP20060077114 申请日期 2006.03.20
申请人 FUJITSU LTD;PFU LTD 发明人 KABEMOTO AKIRA;SHIBATA NAOHIRO;MUTA TOSHIYUKI;SHIMAMURA TAKAYUKI;SUGAWARA HIROHIDE;NISHIOKA JUNJI;SASAKI TAKASATO;SHINOHARA SATOSHI;NAKAYAMA YOUZOU;SAKURAI JUN;ISHIHATA HIROAKI;HORIE KENJI;SHIMIZU TOSHIYUKI
分类号 G06F12/08 主分类号 G06F12/08
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