A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.
申请公布号
WO2006031659(A3)
申请公布日期
2006.07.06
申请号
WO2005US32236
申请日期
2005.09.08
申请人
CAVIUM NETWORKS;BOUCHARD, GREGG, A.;CARLSON, DAVID, A.;KESSLER, RICHARD, E.;HUSSAIN, MUHAMMAD, R.
发明人
BOUCHARD, GREGG, A.;CARLSON, DAVID, A.;KESSLER, RICHARD, E.;HUSSAIN, MUHAMMAD, R.